Memory devices find ubiquitous use in electronic devices, such as in consumer electronics. Memory devices are typically used to store executable code and data for the runtime operation of the electronic device. Many electronic devices stay operating almost continuously for long periods of time, potentially transferring large amounts of data in and out of the memory devices. Thus, it is important that the memory devices perform according to design expectations. However, memory devices are subject to failure from design issues or manufacturing inconsistencies. The failures can show up right after manufacturing as well as in operation of the devices.
Memory testing is used to detect abnormalities or other unexpected behavior in the memory devices. Some errors relate to the operation of the memory subsystem with respect to storing and transferring data. Other errors relate to the operation of the memory subsystem with respect to commands. Traditional testing has been performed through software systems, which have required a constant starting and stopping of the testing to generate the desired high-stress traffic, or through hardware that has very limited data patterns that can be used. Thus, no traditional memory testing has been able to produce high-traffic I/O stress in a way that tests different types of traffic patterns.
Additionally, prior testing systems provide very limited logging or recording of errors, making it difficult to determine what errors were produced. Hardware systems have traditionally been very limited and not logged sufficient data to determine what command/data combination produced an error. Software systems have also not necessarily logged sufficient data to determine what command/data combination produced an error. Even assuming such information could be gathered, software test systems produce traffic that can be reordered prior to execution, which produces uncertainty in what test command/data combination produced a failure.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.